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| TD27C64-25资料 | |
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TD27C64-25 PDF Download |
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File Size : 116 KB
Manufacturer:INTEL/REI Description:possible and when OEBA is HIGH, there is no data transmission from Bn to An possible. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each output reinforces its input. Thus when all other data sources to the two sets of bus lines are at high-impedance, each set of the bus lines will remain at its last state. This type differs from the HC/HCT646 in one extra bus-management function. This is the possibility to transfer stored A data to the B bus and transfer stored B data to the A bus at the same time. The examples at the application information demonstrate all bus management functions. Schmitt-trigger action in the clock inputs makes the circuit highly tolerant to slower clock rise and fall times. |
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| 1PCS | 100PCS | 1K | 10K | ||
| 价 格 | |||||
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型 号：TD27C64-25 厂 家：INTEL/REI 封 装：DIP 批 号：97+ 数 量：2890 说 明：自家库存-房间现货 |
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运 费：20 所在地：深圳市 新旧程度： |
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